Reducing power consumption in portable computers has gained a great deal of attention in the technical community as a result of a set of conflicting user requirements and technological constraints. On the one hand, users would like to operate these portable machines for extended periods of time without access to ac power. This means that such machines must carry their own power sources, i.e., batteries of various types. On the other hand, the total energy stored in such batteries varies almost directly in proportion to their weight. Carrying heavy batteries of course, detracts from the portability of these machines.
Therefore, efforts in the industry have focused in several related areas. First, designing components that consume less power than corresponding components in desktop ac-powered machines; second, detecting when such components are not in use and turning them off or placing them in a lower power consuming mode(s), thus reducing their energy consumption over time; third, using batteries that provide higher energy-to-weight ratios; and last, monitoring the battery and providing the user with alerts and related actions due to the non-linear nature of battery power output as a function of time.
The power management techniques which are currently practiced in the personal computer industry commonly address a combination of one or more of these areas.
U.S. Pat. No. 373,440 to Harper et al. describes the design elements of the POQET computer. The POQET computer has been designed with several low power components such as a low power display element, low power Universal Asynchronous Receive Transmit (UART) component, etc. Additionally, circuitry has been designed that detects the occurrence of certain key events in the system such as the occurrence of a key press on the keyboard, system timer signal, access to a special memory location commonly known as the interrupt vector, etc. The occurrence of any of these events triggers a Non-Maskable Interrupt (NMI) to the processor which then executes a special block of power management code. This code then determines if a change in the power state of the system is warranted. There are several drawbacks to this approach. The scheme of monitoring processor access to certain interrupt vector locations and thereby deducing that the operating system and/or applications are idle, do not apply to advanced processors such as the Intel 80286/386 operating in the so-called protected mode of operation. In these processors, the location of the interrupt vectors is not fixed. As a result, the address lines external to the Central Processing Unit (CPU) cannot be monitored to determine if a particular interrupt is vectored to a particular location. Nor can they be relied upon to work correctly in multi-tasking environments such OS/2 or the more recent Penpoint operating system developed by GO. Corp. for pen-based computers. Such operating systems generally do not issue software interrupts to indicate an idle state. Furthermore, in the advanced processors cited above, the interrupt vectors themselves are not guaranteed to be at any given memory address. Thus, while the POQET design works well with real mode DOS applications, it is inadequate for environments using multi-tasking operating systems executing on processors such as Intel 80386.
U.S. Pat. No. 5,041,964 to Cole et al. describes the power management hardware and software of a GRID laptop computer. In this computer, a standby mode is defined in which power to most parts of the computer except dynamic memory is removed when one of a set of pre-defined events occurs. Power is restored to the system when the user so indicates (by a push button) and there is sufficient battery power to enable proper system functioning. As in the case of the POQET computer, the solutions in this patent break down in a multitasking environment where multiple applications may be active at once as well and in advanced microprocessors, such as the Intel 80386 and compatibles wherein the operating system can (and does) disables NMI interrupts from occurring or re-vectors them to code fragments that may have no knowledge of the nature of NMI being presented to the computer.
In the European Patent Application No. 90311832.1, Watts and Wallace describe an apparatus and a method whereby the CPU clock is reduced whenever a real-time monitor determines that CPU activity level is low. The reduced clock rate results in lower power consumption by the CPU. Such apparatus has been incorporated in highly integrated chip sets available from several chip vendors. However, Watts does not teach how to apply such techniques when multiple CPUs are involved in the operation of a computer. In fact, applying the above methods to a single microprocessor, albeit the main processor, without overt coordination among the principal points of intelligence within the system, may result in a net increase in power consumption.
In International Pat. Appln. No. PCT/US89/05576 to Bolan et al., a method whereby the power consumed by a certain microprocessor can be controlled externally by a chip is described. This chip is designed to consume very low power. As in the previous teachings, such methods and apparatus are readily available from a number of chip vendors. What is missing from the Bolan device is a description of how these mechanisms can be applied to the design of a distributed power managed computing platform such as a pen based tablet computer.
Other implementations, including the IBM laptop computer (the PS/2 L40SX computer), have provided for user specifiable time-outs for various power consuming devices. When no input/output (I/O) activity is perceived for a time-out period on a given component, that component is placed in a low power state. For example, many implementations include a specifiable time out value for the hard file. At the end of the time out period, if no activity has occurred, the device is turned off. However, it must be noted that extra power is expended when the hard file is turned on again and furthermore, the CPU has to wait (wasting energy) while the spin-up is taking place. Studies have shown that no single time out value is likely to result in optimal power conservation. Thus, it is difficult if not impossible for users in general to provide appropriate timeout values for devices in such a portable system.
What is needed is a power management system which can operate effectively in multi-tasking, multiple-CPU systems and advanced processors at a reduced rate.